Accelerated Design for Systems‐on‐Chips
System-on-chips (SoCs) are at the heart of a wide range of computer systems from mobile devices to high-end servers in datacenters. While present-day SoC devices are capable of integrating a billion transistors in a single chip, it is incredibly challenging and time-consuming to design and implement a large-scale SoC due to the rapidly increasing chip complexity and inefficient design methodologies. Zhiru Zhang and Christopher Batten, Electrical and Computer Engineering, are tackling these problems in a multi-university project that involves seven additional researchers from University of California, San Diego (lead institution), as well as University of California, Los Angeles, and University of Michigan.
The goal of the project is to develop novel design methodologies, synthesis algorithms, and tool flows for significantly improving the design productivity and quality of the accelerator-centric SoCs. This effort is part of the Defense Advanced Research Project Agency (DARPA) program on Circuit Realization at Faster Timescales (CRAFT), which aims to achieve an order-of-magnitude improvement over the current time — now over three years — required to design a custom application-specific integrated circuit (ASIC) chip.
A typical SoC contains a number of general-purpose microprocessors and a collection of specialized hardware accelerators to speed up compute-intensive applications such as image processing and machine learning. The primary problem for emerging SoCs is the lack of support for efficient synthesis and the composition of competitive accelerators—despite availability of well-designed processor cores in various implementations.
To overcome these obstacles, Zhang and Batten are investigating two synergistic research themes. Zhang’s research group seeks to enable automated accelerator design by using high-level synthesis, where untimed software programs in C++/SystemC are automatically compiled into optimized register-transfer-level (RTL) hardware models that match the quality of a manual design. In parallel, Batten’s research group is creating a multi-level composition framework (called PyMTL), based on Python programming language, which can be used to enable highly productive composition of processors and accelerators specified at different abstraction levels, such as functional C++/SystemC or RTL SystemVerilog. These approaches will be validated as part of the design and implementation process of a complex, many-core SoC that integrates open-source RISC-V processors and deep neural network accelerators. The team expects to complete the first tape of the SoC chip in 2017.